Computer Architecture
High-density summary of system execution, architectural performance, and hardware-level data management.
Compilation Process
Tokens
The very first step: separating input source code text into discrete, recognizable atomic tokens.
Machine Code
Translates assembly language into final binary machine code the CPU can execute.
Linking
Combines multiple partial programs and external libraries into a single executable file.
Optimization
Arranges symbol tables in memory and generates the final hardware instructions.
Performance & Metrics
Master Formula
CPU Time = IC × CPI × T
Where IC = Instruction Count, CPI = Cycles Per Instruction, T = Clock Period
Improvement Strategies
- Decrease CPI (Better architecture)
- Increase Clock Rate (Better manufacturing)
- Decrease Logic Depth
Performance Rules
- Performance = 1 / Execution Time
- Propagation Delay limits Clock Rate
- Feature Size ↓ = Performance ↑
Register Conventions
| Register | Convention / Purpose | Save Responsibility |
|---|---|---|
| $ra | Return Address (Automatic via jal) |
Caller (if nested) |
| $sp | Stack Pointer (Points to top of stack) | Always maintained |
| $v0 - $v1 | Return Values from procedure | Callee Result |
| $a0 - $a3 | Arguments / Parameters | Caller Prepared |
| $s0 - $s7 | Saved Temporaries (Stable across calls) | Callee Save |
| $t0 - $t9 | Volatile Temporaries | Caller Save |
Data Representation
Number Systems
Binary & Hex
Modern computers use 2 symbols (0, 1) where '1' is high voltage. Hexadecimal uses 16 symbols for compact memory addresses.
Sign Logic
2's Complement
MSB = 0 indicates Positive.
To convert: Flip bits and add 1.
Example: -9 (8-bit) = 11110111.
Byte Order
Endianness
Big-Endian stores MSB at lowest address. Endianness matters when transferring memory blocks between different CPUs.
Exceptions
Overflow States
Unsigned Short (65535) + 1 = Overflow.
Signed Int (-2.1B) - 1 = Underflow.
Signed Short (0) + 1 = OK.
Pipelining & Hazards
Structural Hazard
Hardware resource conflict (two instructions using memory at once). Fixed by doubling interfaces or memory banks.
Data Hazard
Result needed before it's written. Fixed with Forwarding (best) or Stalling (bubbles).
Control Hazard
Branches/Jumps change the PC. Fixed with Branch Prediction or Flushing instructions.
The Load-Use Constraint
A lw instruction updates the register at the end of the pipeline. Since the data is only ready at the MEM stage, a following instruction that uses that data immediately must stall for 1 cycle, as forwarding cannot look into the future.
I/O Peripheral Mapping
Memory Address Map
ASCII Reference
Example Logic
To turn on all 8 LEDs, write 0xff to the LED address. To turn on LEDs 0, 2, and 4, write 0b10101.