4-BIT ADD/SUB CIRCUIT DIAGRAM

Visual Representation with Automatic 2's Complement
OPERATION: 0 + 0 = 0
CIRCUIT STAGES STAGE 1: CONDITIONAL INVERSION A3 A2 A1 A0 B3 B2 B1 B0 SA SB ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ∨ Cin STAGE 2: FIRST ADDITION 4-BIT ADDER (First Stage) A'[3:0] B'[3:0] Cin Sum1[3:0] Cout1 0000 ∧ SA∧SB STAGE 3: CONDITIONAL INCREMENT INCREMENTER (+1) In[3:0] Out[3:0] 0000 MUX 2:1 0 1 SEL FINAL OUTPUT S3 S2 S1 S0 Cout RESULT 0000 Dec: 0
Active Signal (1)
Inactive Signal (0)
Processing Block
Output

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