🎓 EEE 120 Final Exam Cheat Sheet

Digital Logic Fundamentals - Complete Reference Guide

1. Basic Logic Functions ▼

Truth Tables & Gate Symbols

AND Gate

ABOUT
000
010
100
111
OUT = A · B

OR Gate

ABOUT
000
011
101
111
OUT = A + B

NOT Gate

AOUT
01
10
OUT = A'

NAND Gate

ABOUT
001
011
101
110
OUT = (A · B)'

NOR Gate

ABOUT
001
010
100
110
OUT = (A + B)'

XOR Gate

ABOUT
000
011
101
110
OUT = A ⊕ B = A'B + AB'

DeMorgan's Laws

First Law: (A · B)' = A' + B'
NAND can be drawn as OR with inverted inputs
Second Law: (A + B)' = A' · B'
NOR can be drawn as AND with inverted inputs
💡 Key Concept: NAND and NOR gates are universal - you can build ANY logic function using only NAND gates or only NOR gates!

2. Boolean Functions & Minimization ▼

Representation Forms

Sum of Products (SOP)

OR of AND terms

F = A'B'C + AB'C + ABC

Each product term is a minterm

Product of Sums (POS)

AND of OR terms

F = (A+B+C)(A+B'+C)(A'+B+C')

Each sum term is a maxterm

Sum of Minterms

F = Σm(1, 3, 5, 7)

List row numbers where output = 1

Product of Maxterms

F = ΠM(0, 2, 4, 6)

List row numbers where output = 0

Boolean Algebra Laws

Identity: A + 0 = A, A · 1 = A
Null: A + 1 = 1, A · 0 = 0
Idempotent: A + A = A, A · A = A
Complement: A + A' = 1, A · A' = 0
Involution: (A')' = A
Commutative: A + B = B + A, A · B = B · A
Associative: (A + B) + C = A + (B + C)
Distributive: A(B + C) = AB + AC, A + BC = (A + B)(A + C)
Absorption: A + AB = A, A(A + B) = A
DeMorgan: (A + B)' = A'B', (AB)' = A' + B'

Interactive K-Map Tool (4-variable)

Click cells to toggle (1/0) - K-Map for 4 variables
00 01 11 10
00 0 0 0 0
01 0 0 0 0
11 0 0 0 0
10 0 0 0 0
K-Map Tips:
• Group 1s in powers of 2 (1, 2, 4, 8, 16)
• Groups can wrap around edges
• Groups can overlap
• Minimize number of groups
• Each group becomes one product term

Universal Gate Implementation

Using ONLY NAND gates:
• NOT: Connect inputs together: A NAND A = A'
• AND: NAND followed by NAND inverter
• OR: DeMorgan's law: (A' NAND B') = A + B

Using ONLY NOR gates:
• NOT: Connect inputs together: A NOR A = A'
• OR: NOR followed by NOR inverter
• AND: DeMorgan's law: (A' NOR B') = A · B

3. Number Systems & Conversions ▼

Base Conversion Quick Reference

Binary (Base-2)

1010₂ = 8 + 2 = 10₁₀

Powers of 2: 8, 4, 2, 1

Octal (Base-8)

52₈ = 5×8 + 2 = 42₁₀

Group binary in 3s: 101|010

Decimal (Base-10)

42₁₀ = normal numbers

Standard counting system

Hexadecimal (Base-16)

2A₁₆ = 2×16 + 10 = 42₁₀

Group binary in 4s: 0010|1010
A=10, B=11, C=12, D=13, E=14, F=15

2's Complement (Signed Numbers)

2's Complement Representation:
• Most significant bit (MSB) is the sign bit
• 0 = positive, 1 = negative
• Range for n bits: -2^(n-1) to 2^(n-1) - 1
• Example (4 bits): -8 to +7

2's Complement Operation:
1. Invert all bits (1's complement)
2. Add 1

Example: 5 in binary = 0101
1's complement: 1010
Add 1: 1011 = -5 in 2's complement
⚠️ Overflow Detection:
Overflow occurs when:
• Adding two positive numbers gives negative result
• Adding two negative numbers gives positive result
• XOR of carry into MSB and carry out of MSB = 1

NO overflow when:
• Adding numbers with different signs
• Subtracting numbers with same sign

Number Converter Tool

Multi-Base Number Converter
Results will appear here...

4. Higher Order Logic Blocks ▼

Adders & Subtractors

Half Adder

ABSumCarry
0000
0110
1010
1101
Sum = A ⊕ B
Carry = A · B

Full Adder

Sum = A ⊕ B ⊕ Cin
Cout = AB + Cin(A ⊕ B)

Used for multi-bit addition
Cascade Cout to next bit's Cin

Subtractor

Use 2's complement:

A - B = A + (-B)
= A + B' + 1

Invert B and set Cin = 1

Adder/Subtractor

Controlled by mode bit M:

M=0: Add (A + B)
M=1: Sub (A - B)

XOR B with M, use M as Cin

Multiplexers (MUX)

2-to-1 MUX: F = S'A + SB
4-to-1 MUX: F = S1'S0'I0 + S1'S0 I1 + S1 S0'I2 + S1 S0 I3

Implementing Boolean Functions with MUX:
• Connect inputs to data lines
• Use select lines for variables
• n-variable function needs 2^n-to-1 MUX
• Can reduce: use n-1 variables as select, apply remaining variable/constants to data inputs

Decoders

n-to-2^n Decoder:
• Converts binary input to one-hot output
• Each output represents one minterm
• 2-to-4 decoder: 4 outputs (00, 01, 10, 11)

Implementing Boolean Functions:
• Each output is a minterm
• OR together the minterms where F=1
• Example: F = m1 + m3 + m5 → OR outputs Y1, Y3, Y5

ROM Implementation

Programmable ROM (PROM):
• Address lines = input variables
• Data lines = function outputs
• Store truth table directly in ROM
• Can implement multiple functions simultaneously

Example: 3-input function needs 2^3 = 8 addresses
Program ROM with output values for each address

ALU (Arithmetic Logic Unit)

Components:
• Arithmetic unit (adder/subtractor)
• Logic unit (AND, OR, NOT, XOR)
• Function select lines
• Status flags (Zero, Carry, Overflow, Negative)

Common Operations:
• ADD, SUB, INC, DEC
• AND, OR, XOR, NOT
• Shift left/right
• Compare (subtract and check flags)

5. Memory Blocks - Latches & Flip-Flops ▼

SR Latch (Set-Reset)

SR Latch Truth Table

SRQ(t+1)Action
00Q(t)Hold
010Reset
101Set
11XInvalid
⚠️ Never set S=1 and R=1!
Creates unstable state

D Latch

DENQ(t+1)
X0Q(t)
010
111
Level-triggered:
Q follows D when EN=1

Flip-Flops (Edge-Triggered)

D Flip-Flop

DCLKQ(t+1)
0↑0
1↑1
Q(t+1) = D

Stores data on clock edge

T Flip-Flop (Toggle)

TCLKQ(t+1)
0↑Q(t)
1↑Q'(t)
Q(t+1) = T ⊕ Q(t)

Toggles when T=1

JK Flip-Flop

JKCLKQ(t+1)
00↑Q(t)
01↑0
10↑1
11↑Q'(t)
Q(t+1) = JQ' + K'Q

Most versatile flip-flop

Excitation Tables (Flip-Flop Design)

When designing sequential circuits, use these to find required inputs:

D FF Excitation

Q(t)Q(t+1)D
000
011
100
111

T FF Excitation

Q(t)Q(t+1)T
000
011
101
110

JK FF Excitation

Q(t)Q(t+1)JK
000X
011X
10X1
11X0
Asynchronous Set/Reset:
• Override clock signal
• Active immediately (not edge-triggered)
• Set: Forces Q=1
• Reset/Clear: Forces Q=0
• Usually active-low signals
• Used for initialization

Timing Diagrams

Key Concepts:
• Clock edge (↑ rising, ↓ falling)
• Setup time: Data must be stable BEFORE clock edge
• Hold time: Data must be stable AFTER clock edge
• Propagation delay: Time from clock edge to output change

Reading Timing Diagrams:
1. Mark clock edges
2. Check inputs at each edge
3. Determine next state
4. Draw output (delayed by propagation)
5. Watch for setup/hold violations

6. Memory Devices - Counters & Registers ▼

Synchronous Counters

Key Features:
• All flip-flops clock simultaneously
• Same clock signal to all stages
• Faster than ripple counters
• More complex logic but predictable timing

Counter Design Steps:
1. Create state diagram/table
2. Choose flip-flop type (usually T or JK)
3. Build excitation table
4. Derive input equations using K-maps
5. Implement circuit

4-bit Up Counter

Count: 0→1→2→3→...→15→0

Using T flip-flops:
T0 = 1
T1 = Q0
T2 = Q0·Q1
T3 = Q0·Q1·Q2

Modulo-N Counter

Counts 0 to N-1

Add reset logic:
When count = N,
async reset to 0

Example: Mod-10 counter for decimal

Up/Down Counter

Control bit U/D:
U/D=1: Count up
U/D=0: Count down

Modify T equations
with U/D control

Counter with Load

Parallel load input
Load data when
LOAD=1

Use D FFs or
modified JK/T FFs

Registers

Parallel-In/Parallel-Out (PIPO)

All bits loaded/read simultaneously

Used in microprocessor
for data storage

D0-D3 → Q0-Q3
(on clock edge)

Simple D flip-flops in parallel

Serial-In/Parallel-Out (SIPO)

Shift register - data enters one bit at a time

Shift: D → Q0 → Q1 → Q2 → Q3

After 4 clocks,
all bits available
in parallel

Used for serial-to-parallel conversion

Shift Register Operations

  • Shift left: multiply by 2
  • Shift right: divide by 2
  • Rotate: circular shift
  • Serial data transmission

Universal Shift Register

Can perform multiple operations:

  • Hold (no change)
  • Shift left
  • Shift right
  • Parallel load

Select via control bits

💡 Register Applications:
• CPU registers (accumulator, program counter)
• Data buffering
• Data alignment
• Arithmetic operations (shift = multiply/divide by 2)
• Serial communication

7. Finite State Machines (FSM) ▼

Mealy vs Moore Machines

Moore Machine

Output = f(Current State)

Output depends ONLY
on current state

• Outputs change on clock edge
• More states usually needed
• Synchronized outputs
• Easier timing analysis

Mealy Machine

Output = f(Current State, Input)

Output depends on
state AND input

• Outputs can change asynchronously
• Fewer states needed
• Faster response
• More complex timing

FSM Analysis Steps

Given state diagram/table, predict behavior:

1. Identify current state
2. Check input value
3. Find next state from state transition table/diagram
4. Determine output:
- Moore: Look at next state only
- Mealy: Look at current state + input
5. Update state on clock edge
6. Repeat for next clock cycle

State Table Example

Current State Next State Output (Mealy)
X=0 X=1 X=0 X=1
S0 S0 S1 0 0
S1 S2 S0 0 1
S2 S0 S2 1 0
FSM Design Process:
1. Define problem and identify inputs/outputs
2. Draw state diagram
3. Create state table
4. Choose state encoding (binary, Gray, one-hot)
5. Select flip-flop type
6. Create excitation table
7. Derive next-state and output equations (K-maps)
8. Implement circuit
Common FSM Applications:
• Sequence detectors (pattern recognition)
• Traffic light controllers
• Vending machines
• Communication protocols
• CPU control units
• Game state management

8. Microprocessor Architecture ▼

Fetch-Execute Cycle

Two-phase operation cycle:

FETCH Phase:
1. Program Counter (PC) → Address Bus
2. Memory outputs instruction
3. Instruction → Instruction Register (IR)
4. PC = PC + 1 (point to next instruction)

EXECUTE Phase:
5. Decode instruction
6. Read operands from memory/registers
7. Perform operation in ALU
8. Write result to destination
9. Update flags (Z, C, V, N)
10. Return to FETCH

Microprocessor Components

Program Counter (PC)

Holds address of next instruction

  • Increments each cycle
  • Can be loaded (JMP, CALL)
  • Points to instruction memory

Instruction Register (IR)

Holds current instruction

  • Loaded during FETCH
  • Decoded by control unit
  • Contains opcode + operands

Accumulator (ACC)

Primary register for ALU operations

  • Stores ALU results
  • One operand source
  • Can read/write to memory

ALU (Arithmetic Logic Unit)

Performs all computations

  • ADD, SUB operations
  • Logic operations
  • Sets status flags

Data Bus

Bidirectional data transfer

  • Shared by all components
  • Tri-state buffers control access
  • One active driver at a time

Address Bus

Selects memory location

  • Unidirectional (CPU → Memory)
  • Determines address space
  • n bits → 2^n addresses

Control Unit

Coordinates all operations

  • Decodes instructions
  • Generates control signals
  • FSM implementation

Memory

Stores instructions and data

  • Unified memory space
  • READ/WRITE operations
  • Addressed by PC or IR

Data Bus Sharing

Tri-State Control:
• Multiple components connect to data bus
• Only ONE can drive bus at a time
• Others must be in high-impedance (Z) state
• Control unit enables appropriate driver

Example Bus Operations:
1. Memory Read: Memory drives bus → Register reads
2. Memory Write: Register drives bus → Memory reads
3. ALU Output: ALU drives bus → Accumulator reads

⚠️ Bus Conflict: Multiple drivers = undefined state!

Memory Addressing

Addressing Modes:

Immediate: Operand is in instruction
Example: LOAD #5 → ACC = 5

Direct: Address in instruction
Example: LOAD 100 → ACC = Memory[100]

Indirect: Address points to address
Example: LOAD @100 → ACC = Memory[Memory[100]]

Indexed: Base + offset
Example: LOAD 100,X → ACC = Memory[100 + X]

Instruction Format

Typical instruction:
| OPCODE | MODE | ADDRESS/OPERAND |
| 4 bits | 2 bits | 10 bits |

OPCODE: Operation (ADD, SUB, LOAD, etc.)
MODE: Addressing mode
ADDRESS: Memory address or immediate value
Key Microprocessor Concepts:
• Von Neumann architecture (shared memory for instructions/data)
• Sequential execution (fetch → execute → fetch...)
• Stored program concept
• Register transfer level (RTL) operations
• Clock synchronization
• Control signals coordinate all actions

9. Quick Formula Reference ▼

Boolean Algebra

A + 0 = A
A + 1 = 1
A + A = A
A + A' = 1
A · 0 = 0
A · 1 = A
A · A = A
A · A' = 0
(A')' = A
A + AB = A
A(A + B) = A

DeMorgan's Laws

(A · B)' = A' + B'
(A + B)' = A' · B'

(ABC)' = A' + B' + C'
(A+B+C)' = A'·B'·C'

XOR Properties

A ⊕ 0 = A
A ⊕ 1 = A'
A ⊕ A = 0
A ⊕ A' = 1
A ⊕ B = B ⊕ A
(A ⊕ B)' = A ⊕ B' = A' ⊕ B

Number Conversions

Binary → Decimal:
Sum of (bit × 2^position)

Decimal → Binary:
Divide by 2, read remainders

2's Complement:
Invert bits, add 1

Flip-Flop Equations

D FF: Q(t+1) = D
T FF: Q(t+1) = T ⊕ Q
JK FF: Q(t+1) = JQ' + K'Q
SR Latch: Q(t+1) = S + R'Q

Adder Equations

Half Adder:
Sum = A ⊕ B
Carry = A · B

Full Adder:
Sum = A ⊕ B ⊕ Cin
Cout = AB + Cin(A⊕B)

10. Glossary of Terms ▼

Minterm: Product term where each variable appears once (normal or complemented). For n variables, there are 2^n minterms. Example: A'B'C is minterm m0.
Maxterm: Sum term where each variable appears once. Example: (A+B+C) is maxterm M0.
SOP (Sum of Products): Boolean expression as OR of AND terms. Also called disjunctive normal form.
POS (Product of Sums): Boolean expression as AND of OR terms. Also called conjunctive normal form.
Don't Care: Output value that doesn't matter (X). Can be treated as 0 or 1 for optimization.
Karnaugh Map (K-map): Visual method for Boolean function minimization using adjacent cell grouping.
Prime Implicant: Largest possible group in K-map. Essential prime implicants must be included in minimized function.
Propagation Delay: Time for signal to travel through circuit. Causes output change after input change.
Setup Time: Minimum time data must be stable BEFORE clock edge for reliable capture.
Hold Time: Minimum time data must be stable AFTER clock edge for reliable capture.
Tri-State Buffer: Buffer with three output states: 0, 1, and high-impedance (Z). Used for bus sharing.
Multiplexer (MUX): Selects one of many inputs based on select lines. Data selector.
Demultiplexer (DEMUX): Routes single input to one of many outputs. Data distributor.
Decoder: Converts binary input to one-hot output. n inputs → 2^n outputs.
Encoder: Opposite of decoder. 2^n inputs → n outputs. Priority encoder handles multiple active inputs.
Latch: Level-sensitive memory element. Output follows input when enabled.
Flip-Flop: Edge-triggered memory element. Changes output only on clock edge (↑ or ↓).
Synchronous: All changes occur on clock edge. All flip-flops share same clock.
Asynchronous: Changes occur immediately, not synchronized to clock. Example: async reset.
Moore Machine: FSM where output depends only on current state.
Mealy Machine: FSM where output depends on current state AND input.
State Diagram: Visual representation of FSM showing states, transitions, and outputs.
Excitation Table: Shows required inputs to flip-flop for desired state transition. Used in FSM design.
Overflow: Result too large for representation. In 2's complement: adding two positives gives negative, or vice versa.
Carry: Bit generated when sum exceeds bit width. C flag set when unsigned overflow.
Ripple Counter: Asynchronous counter where each FF clocks the next. Slow due to cumulative delay.
Synchronous Counter: All FFs clock simultaneously. Faster but more complex logic.
Register: Group of flip-flops storing multi-bit value. Parallel load/read.
Shift Register: Register where data shifts left or right each clock. Serial data transfer.
PROM: Programmable Read-Only Memory. Stores truth table. Address = inputs, data = outputs.
Von Neumann Architecture: Computer architecture with shared memory for instructions and data.
Harvard Architecture: Separate memory spaces for instructions and data.
Opcode: Operation code. Specifies instruction type (ADD, SUB, LOAD, etc.).
RTL (Register Transfer Level): Hardware description specifying data transfer between registers.
Bus: Shared communication pathway. Multiple devices, one active driver at a time.
Addressing Mode: Method of specifying operand location (immediate, direct, indirect, indexed).

11. Exam Strategy & Tips ▼

General Strategy

Before the exam:
• Review all truth tables - memorize basic gates
• Practice K-maps until automatic
• Know flip-flop excitation tables cold
• Understand timing diagram interpretation
• Review your lab 4 microprocessor thoroughly

During the exam:
• Read entire problem before starting
• Draw diagrams for complex problems
• Show all work for partial credit
• Check your work if time permits
• Watch for overflow conditions in arithmetic
• Verify K-map groupings are powers of 2

Common Mistakes to Avoid

⚠️ K-Map Errors

  • Non-power-of-2 groups
  • Missing wraparound groups
  • Overlapping when unnecessary
  • Missing essential prime implicants

⚠️ Number System Errors

  • Forgetting to check overflow
  • 2's complement vs 1's complement
  • Wrong sign bit interpretation
  • Base conversion arithmetic errors

⚠️ Timing Errors

  • Setup/hold time violations
  • Confusing edge vs level triggering
  • Propagation delay effects
  • Async vs sync operations

⚠️ Logic Errors

  • Incorrect DeMorgan application
  • SR latch invalid state (S=R=1)
  • Bus contention (multiple drivers)
  • State machine transition errors

Quick Pre-Exam Checklist

✓ Can you draw all 6 basic gate symbols?
✓ Do you know all 6 truth tables?
✓ Can you apply DeMorgan's laws instantly?
✓ Can you minimize a 3 or 4 variable function with K-map?
✓ Do you know 2's complement operation?
✓ Can you detect overflow conditions?
✓ Do you understand D, T, JK flip-flop operations?
✓ Can you complete timing diagrams?
✓ Do you know excitation tables for all FFs?
✓ Can you analyze Moore vs Mealy FSMs?
✓ Do you understand fetch-execute cycle?
✓ Can you trace microprocessor data flow?
✓ Do you understand bus sharing with tri-states?
✓ Can you design a simple counter?
🎯 Final Advice:
This exam tests understanding, not just memorization. Focus on WHY things work, not just HOW. Draw pictures, use truth tables, and think step-by-step. You've built a microprocessor in lab - you understand these concepts deeply. Trust your knowledge and work systematically through each problem.

Good luck! You've got this! 💪