Level 0: Course Intel
Welcome, Engineer. Your mission is to master the building blocks of modern computing. From simple gates to complex microprocessors.
Mission Objectives:
- Construct electric circuits for logic operations (Gates).
- Translate between Truth Tables, Boolean Algebra, and Circuits.
- Optimize systems using Karnaugh Maps.
- Implement Sequential Logic (Memory, Flip-Flops).
- Design a Finite State Machine (Capstone).
STATUS: Active
TOOLS: Digital Simulator, Verilog, GTKWave
Level 1: The Terminal & Gates
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Essential Bash/Unix commands for navigating the lab environment[cite: 1652]:
| Command | Action |
|---|
pwd | Print Working Directory (Where am I?) |
ls -al | List all files (including hidden) with details |
cd .. | Go up one directory |
mkdir [name] | Make new directory |
cp [file] [dest] | Copy file |
mv [file] [dest] | Move or Rename file |
rm [file] | Remove file (Careful! No undo) |
chmod 777 [file] | Change permissions (Read/Write/Execute) |
grep "text" [file] | Search for text inside a file |
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Understanding the building blocks[cite: 2031, 2094]:
- AND: Output 1 only if ALL inputs are 1.
- OR: Output 1 if ANY input is 1.
- NOT: Inverts input (0→1, 1→0).
[cite_start]- XOR: Output 1 if inputs are DIFFERENT (odd number of 1s)[cite: 2215].
- NAND/NOR: Universal gates. [cite_start]Any circuit can be built using only NAND or only NOR[cite: 621].
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RULE: You must NEVER tie two outputs of distinct circuits together directly (Short Circuit Risk)[cite: 2008].
Level 2: Boolean Algebra
The math of digital systems. Simplify to survive.
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Basic Laws [cite: 2]
- Annulment:
A . 0 = 0 | A + 1 = 1
- Identity:
A . 1 = A | A + 0 = A
- Idempotent:
A . A = A | A + A = A
- Complement:
A . A' = 0 | A + A' = 1
- Double Negation:
(A')' = A
Advanced Theorems
[cite_start]- DeMorgan's[cite: 23]:
(A + B)' = A' . B'
(A . B)' = A' + B'
"Break the bar, change the sign."
- Distributive:
A(B+C) = AB + AC
- Adjacency/Uniting:
[cite_start]AB + AB' = A [cite: 361]
Karnaugh Maps (K-Maps)
[cite_start]A graphical method to simplify Boolean expressions[cite: 375].
- Create a grid where adjacent cells differ by only 1 bit (Gray Code: 00, 01, 11, 10).
- Group 1s for SOP (Sum of Products) or 0s for POS (Product of Sums).
- Groups must be powers of 2 (1, 2, 4, 8, 16).
[cite_start]- Don't Cares (X): Can be treated as 0 or 1 to make groups larger[cite: 557].
Level 3: Combinational Logic
[cite_start]Multiplexers (MUX) [cite: 1037]
A digital switch. Selects one of N inputs to send to the output.
- Acts like a rotary switch controlled by "Select" lines.
- Formula: For a 2:1 MUX with Select S:
Y = A.S' + B.S
- Can be used to implement any logic function (Function Generator).
[cite_start]Decoders [cite: 1013]
Translates an n-bit code into one of 2^n active outputs.
- Minterm Generator: Selects exactly one output line to be High based on binary input.
- Used for memory addressing and instruction decoding.
[cite_start]Tri-State Buffers [cite: 1300]
Logic gates usually output 0 or 1. Tri-state adds a 3rd state: High-Z (Disconnected).
- Crucial for shared buses (multiple outputs connected to one wire).
- Active High/Low: Controlled by an Enable line.
[cite_start]- Warning: If two devices drive the bus to opposite values (0 and 1) at the same time, a short circuit occurs[cite: 1604].
Level 4: Sequential Logic
Logic with Memory. Output depends on current inputs AND past history.
| Type | Function | Behavior |
|---|
| D Flip-Flop |
Data |
Next state equals Input D at clock edge. Used for storage. |
T Flip-Flop
|
Toggle |
If T=0: Hold State.
If T=1: Toggle State (0→1, 1→0).
|
JK Flip-Flop
|
Universal |
J=0, K=0: Hold
J=0, K=1: Reset (0)
J=1, K=0: Set (1)
J=1, K=1: Toggle
|
Counters & Synchronization
Synchronous Counters: All Flip-Flops share the same Clock.
- Faster and cleaner than Asynchronous (Ripple) counters.
- Logic: A bit toggles only if ALL lower bits are 1. This requires AND gates between stages.
Setup & Hold Time: Data must be stable before the clock edge (Setup) and after the clock edge (Hold) to avoid errors.
Lab Survival Guide
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Common Errors [cite: 898-986]
- Red Wires in GTKWave: Signals are undefined (z or x). Usually means a mismatch in input/output names between your schematic and the testbench.
- "File Not Found": Do NOT use spaces in file or folder names (e.g., "Lab 1" → "Lab1"). Verilog hates spaces.
- Short Circuits: "Several outputs connected to each other." Check if you accidentally connected two gate outputs together without a Tri-State buffer.
- Pin Naming: You must label pins using the specific "Label" property in Digital, not just placing a text box next to it.
Pro-Tips
Asynchronous Reset: Resets the Flip-Flop immediately, ignoring the clock. Useful for initialization.
Submission: Always submit the .v files AND the schematic. Keep your folders organized.