Logic Decoder

HW5 Solution Artifact // System Ready

SYSTEM MESSAGE: This document analyzes the timing diagrams and sequential logic problems from Chapter 6.

Click on any module below to reveal the solution logic.

03 Timing Diagrams: D & T Flip-Flops

The "Why"

  • D Flip-Flop (Data): It's a copycat. When the clock ticks (rising edge), Q copies whatever D is.
  • T Flip-Flop (Toggle): It's a switch. If T=1 at the clock tick, Q flips (0→1 or 1→0). If T=0, Q stays the same.
  • CLR (Clear): The "Emergency Stop". If CLR is active (Low/0), Q becomes 0 immediately. It ignores the clock.
  • PRE (Preset): The "Jump Start". If PRE is active (Low/0), Q becomes 1 immediately.

a) D-FF (No Async Inputs)

Q updates only at rising clock edges.

CLK Edge:   ↑ #1     ↑ #2     ↑ #3     ↑ #4     ↑ #5
Input D:    1        0        1        0        1
Output Q:   1        0        1        0        1

b) D-FF w/ Active Low CLR

Watch the CLR' line. When it dips to 0, Q flatlines to 0 instantly.

Logic: If CLR'=0, Q=0. Else, if CLK ↑, Q=D.
Result: The first high pulse of D is cut short because CLR' goes low during it.

e) T-FF w/ Active Low CLR

Toggles on clock if T=1. Resets if CLR'=0.

1. CLR' active early? -> Q starts at 0.
2. 1st Clock: T is high? -> Q toggles 0->1.
3. CLR' goes low? -> Q forced to 0 immediately.
4. 2nd Clock: T is low? -> Q stays 0.

04 JK Flip-Flop (74112)

Critical Info: Negative Edge & Async

The 74112 is Negative-Edge Triggered (updates when clock goes High->Low) and has Active Low PRE/CLR.

  • J=0, K=0 -> Hold
  • J=0, K=1 -> Reset (0)
  • J=1, K=0 -> Set (1)
  • J=1, K=1 -> Toggle

Case A: J & K Change

Look for the falling edges of the clock.

CLK ↓JKAction
110Set (1)
201Reset (0)
311Toggle

Case C: PRE & CLR Dominance

Async inputs win.

  • Initially PRE' goes Low -> Q jumps to 1.
  • Later CLR' goes Low -> Q drops to 0.
  • In between, if both are High (inactive), check J/K at falling edge.

05 Logic Gate Analysis

Decoding the Circuit

The diagram shows gates feeding the Flip-Flop input. Let's trace the wires:

Top AND Gate: Inputs are X and Q'
Bottom AND Gate: Inputs are X' (via inverter) and Q
OR Gate: Sums the two ANDs

Equation: IN = (X AND Q') OR (X' AND Q)
Simplification: This is the XOR function (X ⊕ Q).
D

Part A: If it's a D-Flip Flop

$$ D = X \oplus Q $$
This means the Next State will be the XOR of Input X and Current State Q.

Result: It acts like a T Flip-Flop!
(If X=1, it toggles. If X=0, it holds).

T

Part B: If it's a T-Flip Flop

$$ T = X \oplus Q $$
Next State = $$ Q \oplus T = Q \oplus (X \oplus Q) $$
$$ = X \oplus (Q \oplus Q) = X \oplus 0 = X $$

Result: It acts like a D Flip-Flop!
(Next state is just X).

06 The "Mystery" Flip-Flop

Rule: If A=0, Q* = B. If A=1, Q* = B'.

b) The Equation

We can write this as a Sum of Products:

Q* = (A' • B) + (A • B')
(This is A XOR B)

a) State Diagram Description

Current State Inputs (AB) Next State Logic
0000A=0, copy B (0)
0011A=0, copy B (1)
0101A=1, inv B (1)
0110A=1, inv B (0)
Repeat logic for Current State = 1

07 State Tables Guide (Prob 7 & 8)

Problems 7 and 8 require building a State Table. Since the exact wire connections are hard to read perfectly from the scan, here is the standard algorithm to solve them:

1

Identify State Variables

Look for the Flip-Flops. Label their outputs (e.g., Q1, Q2). These are your "Present State".

2

Write Logic Equations

Trace the wires backwards from the D inputs of the Flip-Flops.

Example: D1 = (X AND Q2) OR Q1
3

Fill the Table

Create a table with columns: Present State (Q1 Q2), Input (X), Next State (Q1* Q2*), Output (Z).

Sample State Table Layout

Present Input Next State Output
Q1Q2 X D1 -> Q1*D2 -> Q2* Z
000???
001???
010???
...continue for all combinations (00, 01, 10, 11)