Lab 1 — Half Adder • Full Adder • 4‑bit Incrementer • 4‑bit Adder

dark‑ASCII pro guide

Overview

This one‑pager is a complete walkthrough for building, exporting, simulating, and verifying the Lab 1 circuits in Digital → Verilog → GTKWave. It covers the logic (half/full adders), bus wiring with splitters/mergers, the role of *_top.v test benches, stimulus text files, iVerilog commands, wave inspection, edge‑case tests (signed/unsigned overflow), and a ready‑to‑use video script. Dark ASCII vibes included.

Quick win: Keep all files inside a single Lab1/ folder. Digital subcircuits must be discoverable from the current project directory; saving early avoids the “custom component not visible” gotcha.

File Types & What They Do

  • *.dig — Your Digital schematics (source of truth for the logic).
  • *.v — Verilog exports of your schematics (your DUT: Design‑Under‑Test).
  • *_top.v — Test benches that instantiate your DUT, feed inputs, and check outputs.
  • *_stim.txt — Stimulus/expected values consumed by the test benches.
  • *_waves.vcd — Waveform dumps for GTKWave visualization.

Directory Layout (recommended)

Lab1/
Lab1/ ├─ half_adder.dig ├─ half_adder.v ├─ half_adder_top.v ├─ half_adder_stim.txt │ ├─ incrementer.dig ├─ incrementer.v ├─ incrementer_top.v │ ├─ full_adder.dig ├─ full_adder.v ├─ full_adder_top.v ├─ full_adder_stim.txt │ ├─ four_bit_adder.dig ├─ four_bit_adder.v ├─ four_bit_adder_top.v ├─ four_bit_adder_stim.txt │ ├─ screenshots/ (optional) └─ my_answers.pdf (report)

Include the *_top.v and *_stim.txt files in your zip so the grader can re‑run your sims 1:1.

Toolchain & Commands

iVerilog Build + Run

iverilog -o half_adder.exe half_adder.v half_adder_top.v
./half_adder.exe   # Windows: vvp half_adder.exe

iverilog -o incrementer.exe incrementer.v incrementer_top.v
./incrementer.exe

iverilog -o full_adder.exe full_adder.v full_adder_top.v
./full_adder.exe

iverilog -o four_bit_adder.exe four_bit_adder.v four_bit_adder_top.v
./four_bit_adder.exe

GTKWave

gtkwave half_adder_waves.vcd
# or: open GTKWave app → File → Open New Tab → select *_waves.vcd

Pro tip: expand the top‑level module, add only DUT I/Os (e.g., a, b, cin, sum, cout, y, cry, overfl) to keep waves clean.

Task 1‑1 • 1‑Bit Half Adder

Logic

sum = A ⊕ B, cry = A · B

ABcrysum
0000
0101
1001
1110

Export & Sim

  1. Save schematic as half_adder.dig.
  2. Export Verilog → half_adder.v.
  3. Run iVerilog with half_adder_top.v and open half_adder_waves.vcd.
If GTKWave shows mismatches, re‑check pin names exactly (e.g., cry vs carry).

Task 1‑2 • 4‑Bit Incrementer

Design

Build from four half adders. Use splitters/mergers for 4‑bit a → y, controlled by inc. When inc=0, pass‑through; when inc=1, add 1 (propagate carries).

Sim Check

  • For a=0x5, inc=0 ⇒ y=0x5, cry=0.
  • For a=0xF, inc=1 ⇒ y=0x0, cry=1.

Task 1‑3 • 1‑Bit Full Adder

Logic

sum = A ⊕ B ⊕ Cin

cout = majority(A,B,Cin) = A·B + A·Cin + B·Cin

Digital hint: set XOR and OR to 3 inputs in properties.

Stim Bits (full_adder_stim.txt)

Bit map: [7:6 unused][5 cout][4 sum][3 unused][2 cin][1 a][0 b]

Task 1‑4 • 4‑Bit Full Adder

Design

Cascade four 1‑bit full adders, split/merge 4‑bit buses for a and b. Outputs: y[3:0], cout (unsigned carry out), overfl (signed overflow).

Signed vs Unsigned: 4‑bit unsigned is 0..15; two’s‑complement signed is −8..+7. Hardware is identical; interpretation changes how you read cout vs overfl.

Classic Edge Cases

  • Unsigned overflow: F + 1 → cout=1
  • Signed overflow (+ + → −): 7 + 4 → overflows (positive + positive yields negative)
  • Signed overflow (− − → +): (8) + (8) → overflows (negative + negative yields positive)

Testing & Stimulus Files

four_bit_adder_stim.txt bit map

Bit layout per hex nibble (20 bits total):
[19:0] mapping
[19:18 unused] [17 exp_overfl] [16 exp_cout] [15:12 exp_y3..0] [11:9 unused] [8 cin] [7:4 a3..0] [3:0 b3..0]

Each row like E_0_F_F_? is five hex digits separated by underscores for readability.

Example Test Rows & Motives

StimulusWhat it checks
0_0_0_0_0Stuck‑at‑1 sanity (no wires tied high)
0_3_0_1_2Simple add: 1 + 2 → y=3
0_4_1_1_2Carry‑in handling
0_F_0_F_0Max + 0
1_0_0_F_1Smallest unsigned overflow
3_2_0_9_9Signed overflow (−7 + −7)
2_8_0_7_1Smallest signed overflow (+7 + +1)
2_9_1_4_4Signed overflow with Cin (4 + 4 + 1)

Stim Harness Pattern

iverilog -o four_bit_adder.exe four_bit_adder.v four_bit_adder_top.v
./four_bit_adder.exe
# If a mismatch appears, the printed index lines up with your test row number (0..15).

Common Pitfalls

  • Wrong signal names: Use cry (not carry) where required.
  • Custom component not visible: Save a new schematic into Lab1/ first so Components → Custom refreshes.
  • Splitter order: Put MSB on top ([3..0]) consistently for readability.
  • Overfl vs cout: Know which flag means signed vs unsigned overflow.

Quick Sanity Matrix

CaseInputsExpect
Increment wrapa=F, inc=1y=0, cry=1
Unsigned carrya=F, b=1, cin=0cout=1
Signed overflow (+ +)a=7, b=4, cin=0overfl=1
Signed overflow (− −)a=8, b=8, cin=0overfl=1

Submission Zip Checklist

Do not embed your video in the zip. Host it and include the link in your PDF.

Fast Video Script (teleprompter‑ready)

  1. Intro (10–15s): “Hi, I’m Lalo Morales — Lab 1: Half Adder, Full Adder, 4‑bit Incrementer/Adder. I’ll show schematics and GTKWave results.”
  2. Half Adder (~20s): Show XOR/AND, truth table match in waves.
  3. Incrementer (~20s): Four half adders + splitters. inc=0 pass‑through, inc=1 +1, wrap at F→0 with cry=1.
  4. Full Adder (~20s): 3‑input XOR/OR, sum & carry logic demo.
  5. 4‑bit Adder (~30–40s): Cascaded full adders, signed vs unsigned flags, edge‑case tests all pass.
  6. Close (10–15s): “All circuits verified. Thanks!”

FAQ — Why include *_top.v?

They’re the test benches. They instantiate your DUT, feed vectors from *_stim.txt, and auto‑check expected outputs. Without them, the grader can’t re‑run your sims.

GTKWave looks noisy — what do I add?

Add only high‑level I/Os: a, b, cin, y, cout, overfl, inc, cry. Ignore internal s# wires unless debugging.