Datapath Architect
CSE 230
Single-Cycle MIPS Simulator
Instruction Type
R-Type (add, sub, and, or)
Load Word (lw)
Store Word (sw)
Branch Equal (beq)
Operation / Function
Registers (rs, rt, rd)
Immediate / Offset (Hex)
add $t0, $t1, $t2
EXECUTE CYCLE
RESET MACHINE
Theory:
In a single-cycle datapath, the entire instruction (Fetch, Decode, Execute, Memory, Writeback) completes in one clock tick. The
Control Unit
sets the multiplexers based on the Opcode.
PC
IM
RegFile
Control
ALU Ctrl
ALU
DM
Control Signals
RegDst
0
ALUSrc
0
MemtoReg
0
RegWrite
0
MemRead
0
MemWrite
0
Branch
0
ALUOp
00
Register File
Reg
Val (Dec)