Data flows from the Counter to the RAM to fetch instructions. These go to the Controller, which sends signals to the ALU to manipulate data.
The physical assets required to run the trading engine.
A ROM-based Finite State Machine. It holds the "Microcode." It decides, based on the Opcode, which wires to turn on/off. It breaks macro-instructions (like STORE) into micro-steps.
Composed of the Program Counter (PC) and Memory Address Register (MAR). It determines where in the memory vault we are looking. Usually acts sequentially, but can jump randomly for data storage.
Pure muscle. Contains the ALU (Math) and Accumulator (Short-term storage). It has no free will; it only does exactly what the Controller's wires tell it to do.
| Opcode | Mnemonic | Type | Analyst Note (Function) |
|---|---|---|---|
| 0 (0000) | LOAD | DATA IN | Writes RAM data into Accumulator. |
| 1 (0001) | ADD | MATH | Accumulator + RAM Data. |
| 2 (0010) | STOP | HALT | Freezes the PC. End of simulation. |
| 3 (0011) | AND | LOGIC | Bitwise AND. Filters bits. (5 & 3 = 1). |
| 4 (0100) | ZERO | RESET | Subtracts Accumulator from itself (A - A = 0). |
| 5 (0101) | SUB | MATH | 2's Complement Subtraction (A - B). |
| 6 (0110) | STORE | DATA OUT | The only op that writes TO memory. 2 Steps. |
Where the testbench killed the sim because output didn't match Lab 3. Fixed by disabling $finish.
The full duration of the program execution after fixing micro_stim.v.
A critical lesson from this course: Digital (GUI) and Verilog (Code) represent two parallel realities.
rom_vals.hex doesn't automatically update the simulator. You must "Reload" in Digital and "Export" to push changes to Verilog..hex. Verilog uses .txt. You must maintain both, or the simulation reads empty memory (Red 'X' Waves).A comprehensive guide to every wire, register, and control signal in your architecture.