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EEE120: Digital Design Quest
EEE120: Digital Design Quest
EEE120
Digital Design Quest
Insert Coin to Start Learning Logic Design
Overview
Basics & CLI
Boolean Algebra
Comb. Logic
Seq. Logic
Lab FAQ
Level 0: Course Intel
Welcome, Engineer. Your mission is to master the building blocks of modern computing. From simple gates to complex microprocessors.
Mission Objectives:
Construct electric circuits for logic operations (Gates).
Translate between Truth Tables, Boolean Algebra, and Circuits.
Optimize systems using Karnaugh Maps.
Implement Sequential Logic (Memory, Flip-Flops).
Design a Finite State Machine (Capstone).
STATUS: Active
TOOLS: Digital Simulator, Verilog, GTKWave
Level 1: The Terminal & Gates
CMD Line Cheatsheet
[cite_start]Essential Bash/Unix commands for navigating the lab environment[cite: 1652]:
Command
Action
pwd
Print Working Directory (Where am I?)
ls -al
List all files (including hidden) with details
cd ..
Go up one directory
mkdir [name]
Make new directory
cp [file] [dest]
Copy file
mv [file] [dest]
Move or Rename file
rm [file]
Remove file (Careful! No undo)
chmod 777 [file]
Change permissions (Read/Write/Execute)
grep "text" [file]
Search for text inside a file
Universal Logic Gates
[cite_start]Understanding the building blocks[cite: 2031, 2094]:
AND: Output 1 only if ALL inputs are 1.
OR: Output 1 if ANY input is 1.
NOT: Inverts input (0→1, 1→0).
[cite_start]XOR: Output 1 if inputs are DIFFERENT (odd number of 1s)[cite: 2215].
NAND/NOR: Universal gates. [cite_start]Any circuit can be built using only NAND or only NOR[cite: 621].
[cite_start]RULE: You must NEVER tie two outputs of distinct circuits together directly (Short Circuit Risk)[cite: 2008].
Level 2: Boolean Algebra
The math of digital systems. Simplify to survive.
[cite_start]Basic Laws [cite: 2]
Annulment: A . 0 = 0 | A + 1 = 1
Identity: A . 1 = A | A + 0 = A
Idempotent: A . A = A | A + A = A
Complement: A . A' = 0 | A + A' = 1
Double Negation: (A')' = A
Advanced Theorems
[cite_start]DeMorgan's[cite: 23]:
(A + B)' = A' . B'
(A .…
EEE120: Digital Design Quest
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<header style="text-align: center; margin-bottom: 40px;">
<h1 style="font-size: 3rem; margin-bottom: 10px;">EEE120</h1>
<h3 class="pixel-font">Digital Design Quest</h3>
<p>Insert Coin to Start Learning Logic Design</p>
</header>
<nav>
<button class="pixel-btn secondary" onclick="scrollToSection('intro')">Overview</button>
<button class="pixel-btn secondary" onclick="scrollToSection('mod1')">Basics & CLI</button>
<button class="pixel-btn secondary" onclick="scrollToSection('mod3')">Boolean Algebra</button>
<button class="pixel-btn secondary" onclick="scrollToSection('mod4')">Comb. Logic</button>
<button class="pixel-btn secondary" onclick="scrollToSection('mod5')">Seq. Logic</button>
<button class="pixel-btn secondary" onclick="scrollToSection('labs')">Lab FAQ</button>
</nav>
<section id="intro" class="pixel-card">
<h2>Level 0: Course Intel</h2>
<p>Welcome, Engineer. Your mission is to master the building blocks of modern computing. From simple gates to complex microprocessors.</p>
<h3>Mission Objectives:</h3>
<ul>
<li>Construct electric circuits for logic operations (Gates).</li>
<li>Translate between Truth Tables, Boolean Algebra, and Circuits.</li>
<li>Optimize systems using Karnaugh Maps.</li>
<li>Implement Sequential Logic (Memory, Flip-Flops).</li>
<li>Design a Finite State Machine (Capstone).</li>
</ul>
<div style="background:#000; padding:10px; border: 2px solid var(--accent-cyan); margin-top:10px;">
<strong>STATUS:</strong> Active<br>
<strong>TOOLS:</strong> Digital Simulator, Verilog, GTKWave
</div>
</section>
<section id="mod1" class="pixel-card">
<h2>Level 1: The Terminal & Gates</h2>
<button class="accordion pixel-font">CMD Line Cheatsheet</button>
<div class="panel">
[cite_start]<p>Essential Bash/Unix commands for navigating the lab environment[cite: 1652]:</p>
<table>
<tr><th>Command</th><th>Action</th></tr>
<tr><td><code>pwd</code></td><td>Print Working Directory (Where am I?)</td></tr>
<tr><td><code>ls -al</code></td><td>List all files (including hidden) with details</td></tr>
<tr><td><code>cd ..</code></td><td>Go up one directory</td></tr>
<tr><td><code>mkdir [name]</code></td><td>Make new directory</td></tr>
<tr><td><code>cp [file] [dest]</code></td><td>Copy file</td></tr>
<tr><td><code>mv [file] [dest]</code></td><td>Move or Rename file</td></tr>
<tr><td><code>rm [file]</code></td><td>Remove file (Careful! No undo)</td></tr>
<tr><td><code>chmod 777 [file]</code></td><td>Change permissions (Read/Write/Execute)</td></tr>
<tr><td><code>grep "text" [file]</code></td><td>Search for text inside a file</td></tr>
</table>
</div>
<button class="accordion pixel-font">Universal Logic Gates</button>
<div class="panel">
[cite_start]<p>Understanding the building blocks[cite: 2031, 2094]:</p>
<ul>
<li><strong>AND:</strong> Output 1 only if ALL inputs are 1.</li>
<li><strong>OR:</strong> Output 1 if ANY input is 1.</li>
<li><strong>NOT:</strong> Inverts input (0→1, 1→0).</li>
[cite_start]<li><strong>XOR:</strong> Output 1 if inputs are DIFFERENT (odd number of 1s)[cite: 2215].</li>
<li><strong>NAND/NOR:</strong> Universal gates. [cite_start]Any circuit can be built using only NAND or only NOR[cite: 621].</li>
</ul>
[cite_start]<p class="warning"><strong>RULE:</strong> You must NEVER tie two outputs of distinct circuits together directly (Short Circuit Risk)[cite: 2008].</p>
</div>
</section>
<section id="mod3" class="pixel-card">
<h2>Level 2: Boolean Algebra</h2>
<p>The math of digital systems. Simplify to survive.</p>
<div style="display: grid; grid-template-columns: 1fr 1fr; gap: 20px;">
<div>
[cite_start]<h3>Basic Laws [cite: 2]</h3>
<ul>
<li><strong>Annulment:</strong> <code>A . 0 = 0</code> | <code>A + 1 = 1</code></li>
<li><strong>Identity:</strong> <code>A . 1 = A</code> | <code>A + 0 = A</code></li>
<li><strong>Idempotent:</strong> <code>A . A = A</code> | <code>A + A = A</code></li>
<li><strong>Complement:</strong> <code>A . A' = 0</code> | <code>A + A' = 1</code></li>
<li><strong>Double Negation:</strong> <code>(A')' = A</code></li>
</ul>
</div>
<div>
<h3>Advanced Theorems</h3>
<ul>
[cite_start]<li><strong>DeMorgan's[cite: 23]:</strong><br>
<code>(A + B)' = A' . B'</code><br>
<code>(A . B)' = A' + B'</code><br>
<em>"Break the bar, change the sign."</em>
</li>
<li><strong>Distributive:</strong><br>
<code>A(B+C) = AB + AC</code>
</li>
<li><strong>Adjacency/Uniting:</strong><br>
[cite_start]<code>AB + AB' = A</code> [cite: 361]
</li>
</ul>
</div>
</div>
<h3>Karnaugh Maps (K-Maps)</h3>
[cite_start]<p>A graphical method to simplify Boolean expressions[cite: 375].</p>
<ol>
<li>Create a grid where adjacent cells differ by only 1 bit (Gray Code: 00, 01, 11, 10).</li>
<li>Group <strong>1s</strong> for SOP (Sum of Products) or <strong>0s</strong> for POS (Product of Sums).</li>
<li>Groups must be powers of 2 (1, 2, 4, 8, 16).</li>
[cite_start]<li><strong>Don't Cares (X):</strong> Can be treated as 0 or 1 to make groups larger[cite: 557].</li>
</ol>
</section>
<section id="mod4" class="pixel-card">
<h2>Level 3: Combinational Logic</h2>
[cite_start]<h3>Multiplexers (MUX) [cite: 1037]</h3>
<p>A digital switch. Selects one of N inputs to send to the output.</p>
<ul>
<li>Acts like a rotary switch controlled by "Select" lines.</li>
<li><strong>Formula:</strong> For a 2:1 MUX with Select S: <code>Y = A.S' + B.S</code></li>
<li>Can be used to implement any logic function (Function Generator).</li>
</ul>
[cite_start]<h3>Decoders [cite: 1013]</h3>
<p>Translates an n-bit code into one of 2^n active outputs.</p>
<ul>
<li><strong>Minterm Generator:</strong> Selects exactly one output line to be High based on binary input.</li>
<li>Used for memory addressing and instruction decoding.</li>
</ul>
[cite_start]<h3>Tri-State Buffers [cite: 1300]</h3>
<p>Logic gates usually output 0 or 1. Tri-state adds a 3rd state: <strong>High-Z</strong> (Disconnected).</p>
<ul>
<li>Crucial for shared buses (multiple outputs connected to one wire).</li>
<li><strong>Active High/Low:</strong> Controlled by an Enable line.</li>
[cite_start]<li><span class="warning">Warning:</span> If two devices drive the bus to opposite values (0 and 1) at the same time, a short circuit occurs[cite: 1604].</li>
</ul>
</section>
<section id="mod5" class="pixel-card">
<h2>Level 4: Sequential Logic</h2>
<p>Logic with Memory. Output depends on current inputs AND past history.</p>
<button class="accordion pixel-font">Flip-Flop Arsenal</button>
<div class="panel">
<table>
<tr><th>Type</th><th>Function</th><th>Behavior</th></tr>
<tr>
<td><strong>D Flip-Flop</strong></td>
<td>Data</td>
<td>Next state equals Input D at clock edge. Used for storage.</td>
</tr>
<tr>
<td><strong>T Flip-Flop</strong><br></td>
<td>Toggle</td>
<td>
If T=0: Hold State.<br>
If T=1: Toggle State (0→1, 1→0).
</td>
</tr>
<tr>
<td><strong>JK Flip-Flop</strong><br></td>
<td>Universal</td>
<td>
J=0, K=0: Hold<br>
J=0, K=1: Reset (0)<br>
J=1, K=0: Set (1)<br>
J=1, K=1: Toggle
</td>
</tr>
</table>
</div>
<h3>Counters & Synchronization</h3>
<p><strong>Synchronous Counters:</strong> All Flip-Flops share the same Clock.</p>
<ul>
<li>Faster and cleaner than Asynchronous (Ripple) counters.</li>
<li><strong>Logic:</strong> A bit toggles only if ALL lower bits are 1. This requires <strong>AND</strong> gates between stages.</li>
</ul>
<p><strong>Setup & Hold Time:</strong> Data must be stable <em>before</em> the clock edge (Setup) and <em>after</em> the clock edge (Hold) to avoid errors.</p>
</section>
<section id="labs" class="pixel-card" style="border-color: var(--accent-pink);">
<h2 style="color: var(--accent-pink);">Lab Survival Guide</h2>
<div class="panel" style="max-height: none; display: block; background: rgba(255,0,0,0.1);">
[cite_start]<h3>Common Errors [cite: 898-986]</h3>
<ul>
<li><strong>Red Wires in GTKWave:</strong> Signals are undefined (z or x). Usually means a mismatch in input/output names between your schematic and the testbench.</li>
<li><strong>"File Not Found":</strong> Do <strong>NOT</strong> use spaces in file or folder names (e.g., "Lab 1" → "Lab1"). Verilog hates spaces.</li>
<li><strong>Short Circuits:</strong> "Several outputs connected to each other." Check if you accidentally connected two gate outputs together without a Tri-State buffer.</li>
<li><strong>Pin Naming:</strong> You must label pins using the specific "Label" property in Digital, not just placing a text box next to it.</li>
</ul>
<h3>Pro-Tips</h3>
<p><strong>Asynchronous Reset:</strong> Resets the Flip-Flop immediately, ignoring the clock. Useful for initialization.</p>
<p><strong>Submission:</strong> Always submit the .v files AND the schematic. Keep your folders organized.</p>
</div>
</section>
<footer>
<p>EEE120 Course Guide Generated via AI Analysis</p>
<p>CREDITS: Module PDF Sources 1, 2, 3, 4 & Lab FAQs</p>
<p class="pixel-font">GAME OVER</p>
</footer>
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