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Digital Logic Solutions // HW5

Digital Logic Solutions // HW5













Logic Decoder


HW5 Solution Artifact // System Ready






SYSTEM MESSAGE: This document analyzes the timing diagrams and sequential logic problems from Chapter 6.

Click on any module below to reveal the solution logic.







03 Timing Diagrams: D & T Flip-Flops








The "Why"


D Flip-Flop (Data): It's a copycat. When the clock ticks (rising edge), Q copies whatever D is.

T Flip-Flop (Toggle): It's a switch. If T=1 at the clock tick, Q flips (0→1 or 1→0). If T=0, Q stays the same.

CLR (Clear): The "Emergency Stop". If CLR is active (Low/0), Q becomes 0 immediately. It ignores the clock.

PRE (Preset): The "Jump Start". If PRE is active (Low/0), Q becomes 1 immediately.







a) D-FF (No Async Inputs)

Q updates only at rising clock edges.


CLK Edge:   ↑ #1     ↑ #2     ↑ #3     ↑ #4     ↑ #5
Input D:    1        0        1        0        1
Output Q:   1        0        1        0        1






b) D-FF w/ Active Low CLR

Watch the CLR' line. When it dips to 0, Q flatlines to 0 instantly.


Logic: If CLR'=0, Q=0. Else, if CLK ↑, Q=D.
Result: The first high pulse of D is cut short because CLR' goes low during it.






e) T-FF w/ Active Low CLR

Toggles on clock if T=1. Resets if CLR'=0.


1. CLR' active early? -> Q starts at 0.
2. 1st Clock: T is high? -> Q toggles 0->1.
3. CLR' goes low? -> Q forced to 0 immediately.
4. 2nd Clock: T is low? -> Q stays 0.
















04 JK Flip-Flop (74112)








Critical Info: Negative Edge & Async

The 74112 is Negative-Edge Triggered (updates when clock goes High->Low) and has Active Low PRE/CLR.


J=0, K=0 -> Hold

J=0, K=1 -> Reset (0)

J=1, K=0 -> Set (1)

J=1, K=1 -> Toggle






Case A: J & K Change

Look for the falling edges of the clock.


CLK ↓
J
K
Action


1
1
0
Set (1)


2
0
1
Reset (0)


3
1
1
Toggle







Case C: PRE & CLR Dominance

Async inputs win.


Initially PRE' goes Low -> Q jumps to 1.

Later CLR' goes Low -> Q drops to 0.

In between, if both are High (inactive), check J/K at falling edge.














05 Logic Gate Analysis






Decoding the Circuit

The diagram shows gates feeding the Flip-Flop input.…