Back Lab 1 Guide • Half Adder → Full Adder → 4‑bit Incrementer/Adder • Digital + Verilog + GTKWave Electronics
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Lab 1 Guide • Half Adder → Full Adder → 4‑bit Incrementer/Adder • Digital + Verilog + GTKWave

Lab 1 Guide • Half Adder → Full Adder → 4‑bit Incrementer/Adder • Digital + Verilog + GTKWave








Lab 1 — Half Adder • Full Adder • 4‑bit Incrementer • 4‑bit Adder

dark‑ASCII pro guide





Overview
Files & Roles
Toolchain
Task 1‑1
Task 1‑2
Task 1‑3
Task 1‑4
Testing & Stimulus
Pitfalls
Zip Checklist
Video Script
FAQ








Overview

This one‑pager is a complete walkthrough for building, exporting, simulating, and verifying the Lab 1 circuits in Digital → Verilog → GTKWave. It covers the logic (half/full adders), bus wiring with splitters/mergers, the role of *_top.v test benches, stimulus text files, iVerilog commands, wave inspection, edge‑case tests (signed/unsigned overflow), and a ready‑to‑use video script. Dark ASCII vibes included.

Quick win: Keep all files inside a single Lab1/ folder. Digital subcircuits must be discoverable from the current project directory; saving early avoids the “custom component not visible” gotcha.






File Types & What They Do


*.dig — Your Digital schematics (source of truth for the logic).

*.v — Verilog exports of your schematics (your DUT: Design‑Under‑Test).

*_top.v — Test benches that instantiate your DUT, feed inputs, and check outputs.

*_stim.txt — Stimulus/expected values consumed by the test benches.

*_waves.vcd — Waveform dumps for GTKWave visualization.





Directory Layout (recommended)


Lab1/

Lab1/
├─ half_adder.dig
├─ half_adder.v
├─ half_adder_top.v
├─ half_adder_stim.txt
│
├─ incrementer.dig
├─ incrementer.v
├─ incrementer_top.v
│
├─ full_adder.dig
├─ full_adder.v
├─ full_adder_top.v
├─ full_adder_stim.txt
│
├─ four_bit_adder.dig
├─ four_bit_adder.v
├─ four_bit_adder_top.v
├─ four_bit_adder_stim.txt
│
├─ screenshots/ (optional)
└─ my_answers.pdf (report)



Include the *_top.v and *_stim.txt files in your zip so the grader can re‑run your sims 1:1.







Toolchain & Commands



iVerilog Build + Run

Copyiverilog -o half_adder.exe half_adder.v half_adder_top.v
./half_adder.exe # Windows: vvp half_adder.exe

iverilog -o incrementer.exe incrementer.v incrementer_top.v
./incrementer.exe

iverilog -o full_adder.exe full_adder.v full_adder_top.v
./full_adder.exe

iverilog -o four_bit_adder.exe four_bit_adder.v four_bit_adder_top.v
./four_bit_adder.exe



GTKWave

Copygtkwave half_adder_waves.vcd
# or: …